Conversion of Sparse Matrix to Band Matrix Using FPGA for High-Performance Computing
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Low power and high computation speed with less memory storage are essential for a real-time scientific computational application. Applications such as image processing, power system, finite element system, circuit design, data from sensors utilize a large amount of data. An arithmetic operation on a general matrix can take more time and require more memory to store the data. Band matrices could be a key component in many scientific computing applications. A special sparse matrix, i.e., band matrix, has small bandwidth and minimizes storage, efficiently leading to less computation time. This paper presents a design and hardware implementation to convert a sparse matrix to a band matrix for a minimum matrix bandwidth using an existing Reverse Cuthill-Mckee algorithm (RCM).
The Field Programmable Gate Array (FPGA) hardware design helps to solve larger data problems in terms of memory storage, speeding up many sparse matrix operations. Based on the FPGA hardware, the design and implementation, and synthesis are carried out by keeping in mind the architecture, area, and power requirements. In this research, the Vivado High-Level Synthesis (HLS) language is used. Intellectual Property (IP) generated from HLS will be linked to the ZYNQ processor, which can be implemented in a large system and have flexibility in FPGA based design. For the verification and reporting of this designed system, MATLAB is used.