Optimized Sparse Matrix Operations and Hardware Implementation using FPGA
Date
2021-08
Authors
Murthy, Dinesh Kumar
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Abstract
The increasing importance of sparse connectivity representing real-world data has been exemplified by the recent work in areas of graph analytics, machine language, and high-performance. Sparse matrices are the critical component in many scientific
computing applications, where increasing the sparse matrix operation efficiency can contribute significantly to improve overall system efficiency. The primary challenge is handling the nonzero values efficiently by storing them using specific storage format and performing matrix operations, taking advantage of the sparsity. This thesis proposes an optimized algorithm for performing sparse matrix operations concerning storage and
hardware implementation on FPGAs. The proposed thesis work includes simple arithmetic operations to complex decomposition algorithms using Verilog design. Operations of the sparse matrix are tested with testbench matrices of different size, sparsity percentage, and sparsity pattern. The design was able to achieve low latency, high throughput, and minimal resources utilization when compared with the conventional matrix algorithm. Our approach enables solving more significant problems than previously possible, allowing FPGAs to more interesting issues.
Description
Keywords
Sparse matrix operations, Hardware implementation, FPGA, Optimization
Citation
Murthy, D. K. (2021). <i>Optimized sparse matrix operations and hardware implementation using FPGA</i> (Unpublished thesis). Texas State University, San Marcos, Texas.