Chip Characterization: Man-hour Reduction and Increased Functionality Testing with Automation Improvements

Abstract

Chip design expansion increases linearly with new products, thus device characterization tests have increased exponentially and created a chip design bottleneck. If there is only one function (herein designated as “A”), “A” need only test function “A.” If there are two functions, “A” and “B”, then test sets will be “A,” “B,” “AB,” and “BA.” If there are three functions, ”A,” “B,” and “C,” then test sets “A,” “B,” “C,” “AB,” “AC”, “BA,” “BC,” “CA,” “CB,” “ABC,” and so forth. The objective of this thesis is to automate manual test procedures so that design bottlenecks can be eliminated and device characterization can be improved. In achieving the stated objective, it will be necessary to develop a framework that attains and integrates commonality, maintainability, and reusability.