|dc.description.abstract||Excessive power consumption affects the reliability of processors, requires expensive cooling mechanisms, reduces battery lifetime, and causes extensive damage to the device. Hence, managing the power consumption and performance of processors is an important aspect of chip design.
This research aims to achieve efficient multi-core power monitoring and control via operating system based power-aware task scheduling. There is a significant amount of research on efficient OS task scheduling algorithms involving performance criteria like execution time. However, there is considerable scope for developing power and performance efficient scheduling policies.
The main objectives of power aware scheduling are: 1) lowering processor's power consumption level, 2) maintaining the system within an allowable power envelope, 3) supporting hot-spot elimination, and 4) balancing the power consumption across processors. These objectives are achieved by incorporating power characteristics into the scheduling policies. It is desired, however, to achieve these goals without drastically affecting performance.
Generally, intra-core task scheduling policies engage in selecting a task to execute from a queue of ready tasks. On the other hand, inter-core task migration policies refer to the process of moving ready tasks from one processor's queue to another processor's queue. A special case of task migration is known as task stealing. Task stealing policies involve the concept of a starving thief processor stealing a task from a loaded victim processor. Therefore, Task Scheduling policies in general refer to the broad area of intra-core task scheduling and inter-core task stealing policies.
This study concentrates on the two steps that are part of the OS task scheduling in a multi-core system, namely, intra-core task scheduling and inter-core task stealing. In an attempt to achieve maximum power efficiency, both the intra-core task scheduling and inter-core task stealing policies have been manipulated to consider the power aspects of processors and tasks.
Moreover, this thesis explores classical single-core task scheduling policies such as Round Robin (RR), Shortest Remaining Time First (SRTF), and Highest Response Ratio Next (HRRN) by employing power features into the task selection policy. A power-based intra-core scheduling policy called Highest Energy-delay-product based Cost function Next (HECN) that integrates HRRN and Energy-Delay-Product into the selection criteria is determined to be the most promising power efficient policy.
In addition, power aware techniques for task migration in a multi-core system are investigated. Ten variants of the work stealing policy have been devised. Under these policies, a thief processor considers both the power and the performance attributes of the system in the process of selecting a victim processor. In addition, the thief's task selection criterion includes power aspects of tasks that reside on potential victims.
A simulator has been developed to enable efficient evaluation of the formulated single and multi-core scheduling policies. The simulator features the ability to perform power aware and / or power agnostic intra-core task scheduling and inter-core task stealing while operating at a relatively high level of abstraction. Simulations have been performed for different task generation scenarios to thoroughly exploit all scheduling policies. The simulator has the capability to provide performance measures of important metrics such as energy consumption level, turnaround time, and completion time so that the effect on power and performance can be analyzed.
The experiments conducted show that the intra-core HECN scheduling policy coupled with power aware inter-core stealing policies have good potential for power efficient task scheduling with tolerable effect on performance.||