Polygon Reduction Algorithm for Layout Extraction and Parasitic Signal Calculation
| dc.contributor.advisor | Hazlewood, Carol | |
| dc.contributor.author | Zaporojets, Olga V. | |
| dc.date.accessioned | 2019-11-08T14:01:09Z | |
| dc.date.available | 2019-11-08T14:01:09Z | |
| dc.date.issued | 2002-05 | |
| dc.description.abstract | The design of a specific polygon reduction algorithm to be applied to the process of layout extraction is proposed. The algorithm is tested with the Star-RCXT parasitic signal extraction tool and the impact of the reduction algorithm is measured and analyzed. There are many polygon reduction algorithms but they all are application specific and not particularly suitable for the extraction tool. The research objective is to generate a reduction algorithm which may be used by any Electric Design Automation (EDA) layout extraction tool and which most effectively achieves a goal of maximum reduction of the number of extracted polygons and preserves connectivity and area of the polygons for further processing. The reduction algorithm described in this paper is created as a local greedy method with some history back tracking for the combined error control. It is used with trapezoidation processing, which is the most common way to perform polygon extraction by EDA tools. The reduction method developed is very general yet effective since it allows not only reduction of “not carrying information” trapezoids but trapezoids with a slight topology modification, fixing trapezoids displacements which may result from the lack of precision of a layout tool used to generate data. The trapezoidation and reduction algorithm was implemented in C++ and tested on real design data. The worst time reduction complexity is 0(n2) and the worst time complexity of the trapezoidation and reduction performed together is 0(n2 log2n). The reduction of the number of polygons achieved in the most accurate mode is 73% and it may be much higher if the less accurate mode is used. The accuracy tests displayed that extracted data produced using reduction algorithm is identical to the extraction data produced without reduction. Total reduction of the parasitic signal extraction time of the designs in the most accurate reduction mode is approximately 26%, which is very significant for the tape out time constraints in the competitive high technology industry. Implemented as a “stand alone” tool, the reduction algorithm may be used not only with Star RCXT tool created by Avant!, but with any other extraction tool. | |
| dc.description.department | Computer Science | |
| dc.format | Text | |
| dc.format.extent | 175 pages | |
| dc.format.medium | 1 file (.pdf) | |
| dc.identifier.citation | Zaporojets, O. V. (2002). Polygon reduction algorithm for layout extraction and parasitic signal calculation (Unpublished thesis). Southwest Texas State University, San Marcos, Texas. | |
| dc.identifier.uri | https://hdl.handle.net/10877/8743 | |
| dc.language.iso | en | |
| dc.subject | computer algorithms | |
| dc.subject | polygons | |
| dc.title | Polygon Reduction Algorithm for Layout Extraction and Parasitic Signal Calculation | |
| dc.type | Thesis | |
| thesis.degree.department | Computer Science | |
| thesis.degree.grantor | Southwest Texas State University | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Computer Science |
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