Open Source Python based Hardware Verification Tool
| dc.contributor.advisor | Aslan, Semih | |
| dc.contributor.author | Aich, Debasmita | |
| dc.contributor.committeeMember | Stapleton, William A. | |
| dc.contributor.committeeMember | Valles, Damian | |
| dc.date.accessioned | 2021-08-12T13:50:53Z | |
| dc.date.available | 2021-08-12T13:50:53Z | |
| dc.date.issued | 2021-08 | |
| dc.description.abstract | <p>Today a need for more efficient and time-effective hardware/chip verification has become a necessity due to the increasing size and complexity of several electronic devices. Everyone wants to develop new technology, and for this urge, every day, something new is planned and designed in the Silicon Industry. Due to the rapid growth of technology and competition in between the industry, more and more complex and sophisticated electronic devices are being developed for various areas like medical, entertainment, defense industry, Space centers, etc.</p> <p>The creation of these electronic devices needs complex designs and a high level of verification on time. Many verification methodologies use timing simulations, but unfortunately, it is the most time-consuming for several designs. The main purpose of chip verification is to catch bugs in the designs in the most convenient way, and the earliest the bug is found, the project can be ready for TAPE-OUT. The purpose of this research is to design a Verification tool using Python and cocotb to reduce the need of building multiple testbenches and to reduce some of the hurdles like not able to catch bugs at the earliest stages of design phase which comes in the way of chip Verification. This tool called Varifog catches the bugs at the earliest stages of the design phase without using any testbenches and hence can save a lot of time for Verification Engineers who write multiple basic tests for the designs just to check if the design is generating expected outputs or if any chain/fublet is broken. Verifog is tested with simple as well as complex Verilog design files and is efficiently catching RTL bugs at the earliest design phases.</p> | |
| dc.description.department | Engineering | |
| dc.format | Text | |
| dc.format.extent | 139 pages | |
| dc.format.medium | 1 file (.pdf) | |
| dc.identifier.citation | Aich, D. (2021). <i>Open source python based hardware verification tool</i> (Unpublished thesis). Texas State University, San Marcos, Texas. | |
| dc.identifier.uri | https://hdl.handle.net/10877/14292 | |
| dc.language.iso | en | |
| dc.subject | Verification | |
| dc.subject | Python | |
| dc.subject | Hardware-based tool | |
| dc.subject | Design | |
| dc.subject | System verilog | |
| dc.subject | Cocotb | |
| dc.subject | Verilog | |
| dc.title | Open Source Python based Hardware Verification Tool | |
| dc.type | Thesis | |
| thesis.degree.department | Engineering | |
| thesis.degree.discipline | Engineering | |
| thesis.degree.grantor | Texas State University | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science |