Optimized Sparse Matrix Operations and Hardware Implementation using FPGA

Simple item page
dc.contributor.advisorAslan, Semih
dc.contributor.authorMurthy, Dinesh Kumar
dc.contributor.committeeMemberTamir, Dan
dc.contributor.committeeMemberStapleton, Bill
dc.contributor.committeeMemberJimenez, Jesus
dc.date.accessioned2021-07-22T16:55:53Z
dc.date.available2021-07-22T16:55:53Z
dc.date.issued2021-08
dc.description.abstractThe increasing importance of sparse connectivity representing real-world data has been exemplified by the recent work in areas of graph analytics, machine language, and high-performance. Sparse matrices are the critical component in many scientific computing applications, where increasing the sparse matrix operation efficiency can contribute significantly to improve overall system efficiency. The primary challenge is handling the nonzero values efficiently by storing them using specific storage format and performing matrix operations, taking advantage of the sparsity. This thesis proposes an optimized algorithm for performing sparse matrix operations concerning storage and hardware implementation on FPGAs. The proposed thesis work includes simple arithmetic operations to complex decomposition algorithms using Verilog design. Operations of the sparse matrix are tested with testbench matrices of different size, sparsity percentage, and sparsity pattern. The design was able to achieve low latency, high throughput, and minimal resources utilization when compared with the conventional matrix algorithm. Our approach enables solving more significant problems than previously possible, allowing FPGAs to more interesting issues.
dc.description.departmentEngineering
dc.formatText
dc.format.extent165 pages
dc.format.medium1 file (.pdf)
dc.identifier.citationMurthy, D. K. (2021). <i>Optimized sparse matrix operations and hardware implementation using FPGA</i> (Unpublished thesis). Texas State University, San Marcos, Texas.
dc.identifier.urihttps://hdl.handle.net/10877/14054
dc.language.isoen
dc.subjectSparse matrix operations
dc.subjectHardware implementation
dc.subjectFPGA
dc.subjectOptimization
dc.titleOptimized Sparse Matrix Operations and Hardware Implementation using FPGA
dc.typeThesis
thesis.degree.departmentEngineering
thesis.degree.disciplineEngineering
thesis.degree.grantorTexas State University
thesis.degree.levelMasters
thesis.degree.nameMaster of Science

Files

Original bundle

Now showing 1 - 1 of 1
Thumbnail Image
Name:
MURTHY-THESIS-2021.pdf
Size:
5.16 MB
Format:
Adobe Portable Document Format
Download

License bundle

Now showing 1 - 2 of 2
No Thumbnail Available
Name:
PROQUEST_LICENSE.txt
Size:
4.53 KB
Format:
Plain Text
Description:
Download
No Thumbnail Available
Name:
LICENSE.txt
Size:
2.97 KB
Format:
Plain Text
Description:
Download

Collections

Graduate Theses and Dissertations