|dc.description.abstract||Modeling a microprocessor results in defining its architecture (instruction set, registers, memory hierarchy, etc.), its microarchitecture (pipelines, branch prediction,etc.), and its hardware (gate level logic, cycleaccurate timing, circuitry, etc.).
Several software based modeling tools exist for describing and
facilitating simulation of the microprocessor model. Simulation at
the hardware or system level in order to estimate power consumption is time consuming due to the complexity and size of the system level model. Simulation at the architecture level is significantly faster, but less detailed. If the simulation trace data generated by the architecture simulation are highly correlated with the operations of system level simulation, only part of the benchmark test may be required for simulation at the system level. In other words, if a number of trace sections, or slices, are identified as similar, then the corresponding instruction stream slices will yield similar power estimation results when simulated at the system level. Thus,identifying similar slices of the architectural simulation trace data may reduce the amount of benchmark testing required at the system level. Cluster analysis is used to identify similar slices of the architectural simulation trace data, resulting in clusters of slices. Feature selection is used to eliminate less relevant features within the trace data, allowing for better clustering. Finally, domain-specific knowledge is applied by prioritizing feature selection towards known power-affecting features. Experimentation demonstrates the effectiveness of the cluster analysis, feature selection, and use of power affecting features in order to achieve accurate power estimation while reducing the amount of benchmark testing required at the system level of simulation.||en_US